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this is information on a product in full production. september 2012 doc id 12943 rev 10 1/38 1 m24m01-r m24m01-df 1-mbit serial i2c bus eeprom datasheet ? production data features compatible with all i 2 c bus modes: ?1 mhz ? 400 khz ? 100 khz memory array: ? 1 mbit (128 kbytes) of eeprom ? page size: 256 bytes ? additional write lockable page (m24m01-d order codes) single supply voltage and high speed: ? 1 mhz clock from 1.7 v to 5.5 v write: ? byte write within 5 ms ? page write within 5 ms operating temperature range: from -40 c up to +85 c random and sequential read modes write protect of the whole memory array enhanced esd/latch-up protection more than 4 million write cycles more than 200-year data retention packages: ? rohs compliant and halogen-free (ecopack ? ) so8 (mn) 150 mil width tssop8 (dw) wlcsp (cs) www.st.com
contents m24m01-r m24m01-df 2/38 doc id 12943 rev 10 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 write identification page (m24m01-d only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 lock identification page (m24m01-d only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 18 5.1.6 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 19 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m24m01-r m24m01-df contents doc id 12943 rev 10 3/38 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 read identification page (m24m01-d only) . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 read the lock status (m24m01-d only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of tables m24m01-r m24m01-df 4/38 doc id 12943 rev 10 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. operating conditions (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. operating conditions (voltage range f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. dc characteristics (m24m01-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. dc characteristics (m24m01-f, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 15. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 16. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32 table 17. so8n ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 33 table 18. m24m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package mechanical data 35 table 19. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
m24m01-r m24m01-df list of figures doc id 12943 rev 10 5/38 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. wlcsp connections for m24m01 dfcs6tp/k (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 10. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. so8n ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 33 figure 17. m24m01 dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package outline . . . . . . . . 34
description m24m01-r m24m01-df 6/38 doc id 12943 rev 10 1 description the m24m01 is a 1 mb i 2 c-compatible eeprom (electrica lly erasable programmable memory) organized as 128 k 8 bits. the m24m01-r can operate with a supply voltage from 1.8 v to 5.5 v, and the m24m01-df can operate with a supply voltage from 1.7 v to 5.5 v, over an ambient temperature range of ?40c / +85c. the m24m01-d offers an additional page, named the identification page (256 bytes). the identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram table 1. signal names signal name function direction e1, e2 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage v ss ground 3$! 6 ## 7# 3#, 6 33 % % -xxx .47
m24m01-r m24m01-df description doc id 12943 rev 10 7/38 figure 2. 8-pin package connections 1. du: don't use (if connected, must be connected to v ss ) 2. see section 9: package mechanical data for package dimensions, and how to identify pin 1. figure 3. wlcsp connections for m24m01 dfcs6tp/k (top view, marking side, with balls on the underside) 3. du: don't use (if connected, must be connected to v ss ) 4. see section 9: package mechanical data for package dimensions, and how to identify pin 1. -36 3$! 6 33 3#, 7# % $5 6 ## % ms30966v2 v cc sda v ss wc scl du e1 e2
signal description m24m01-r m24m01-df 8/38 doc id 12943 rev 10 2 signal description 2.1 serial clock (scl) the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be connected ( figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e1, e2) these input signals are used to set the value that is to be looked for on the two bits (b3, b2) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code as shown in figure 4 . when not connected (left floating), these inputs are read as low (0,0). figure 4. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. write operations are enabled when write control (wc ) is either driven low or left floating. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
m24m01-r m24m01-df signal description doc id 12943 rev 10 9/38 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters) . in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters) and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not respond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ). in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the internal reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop cond ition, assuming that there is no internal write cycle in progress).
memory organization m24m01-r m24m01-df 10/38 doc id 12943 rev 10 3 memory organization the memory is organized as shown below. figure 5. block diagram -36 7# #ontrollogic (ighvoltage generator )/shiftregister !ddressregister andcounter $ata register page 8decoder 9decoder )dentificationpage % % 3#, 3$!
m24m01-r m24m01-df device operation doc id 12943 rev 10 11/38 4 device operation the device supports the i 2 c protocol. this is summarized in figure 6 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 6. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
device operation m24m01-r m24m01-df 12/38 doc id 12943 rev 10 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer instruction. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is fo llowed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
m24m01-r m24m01-df device operation doc id 12943 rev 10 13/38 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). when the device select code is received, the device only responds if the chip enable address is the same as the value on its chip enable e2,e1 inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, the device deselects itself from the bus, and goes into standby mode. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e2,e1 are compared against the ex ternal pin on the memory device. address bit rw when accessing the memory b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 e2 e1 a16 rw when accessing the identification page 1011 e2e1x (3) 3. x = don?t care. rw
instructions m24m01-r m24m01-df 14/38 doc id 12943 rev 10 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/w bit (rw ) reset to 0. the device acknowledges this, as shown in figure 7 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. the 128 kbytes (1 mb) are addressed with 17 addre ss bits, the 16 lower address bits being defined by the two address bytes and the most significant address bit (a16) being included in the device select code (see ta b l e 2 ). when the bus master generates a stop condition immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 8 . table 3. most significant address byte a15 a14 a13 a12 a11 a10 a9 a8 table 4. least significant address byte a7 a6 a5 a4 a3 a2 a1 a0
m24m01-r m24m01-df instructions doc id 12943 rev 10 15/38 5.1.1 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 7 . figure 7. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106d page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
instructions m24m01-r m24m01-df 16/38 doc id 12943 rev 10 5.1.2 page write the page write mode allows up to 256 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, b16-b8, ar e the same. if more bytes are sent than will fit up to the end of the page, a ?roll-over? occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack, as shown in figure 8 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bus master generating a stop condition. figure 8. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120d page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
m24m01-r m24m01-df instructions doc id 12943 rev 10 17/38 5.1.3 write identification page (m24m01-d only) the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. it is written by issuing the write identification page instruction. this instruction uses the same protocol and format as page write (into memory array), except for the following differences: device type identifier = 1011b msb address bits a16/a8 are don't care except for address bit a10 which must be ?0?. lsb address bits a7/a0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 5.1.4 lock identification page (m24m01-d only) the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is similar to byte write (into memory array) with the following specific conditions: device type identifier = 1011b address bit a10 must be ?1?; all other address bits are don't care the data byte must be equal to the binary value xxxx xx1x, where x is don't care
instructions m24m01-r m24m01-df 18/38 doc id 12943 rev 10 5.1.5 ecc (error correcti on code) and write cycling the error correction code (ecc) is an internal logic function which is transparent for the i 2 c communication protocol. the ecc logic is implemented on each group of four eeprom bytes (a) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on groups of four bytes, a single byte can be written/cycled independently. in this case, the ecc function also writes/cycles the three other bytes located in the same group (a) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined table 10: cycling performance by groups of four bytes . a. a group of four bytes is located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
m24m01-r m24m01-df instructions doc id 12943 rev 10 19/38 5.1.6 minimizing write del ays by polling on ack the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 9 , is: initial condition: a writ e cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 9. write cycle polling flowchart using ack 1. the seven most significant bits of the device se lect code of a random read (bottom right box in the figure) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the figure). write cycle in progress ai 01847 d ai01847e next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write cperation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no startcondition continue the write operation continue the random read operation
instructions m24m01-r m24m01-df 20/38 doc id 12943 rev 10 5.2 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its standby mode. figure 10. read mode sequences start dev sel * byte addr byte addr start dev sel data out 1 ai01105d data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequention random read start dev sel * data out1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24m01-r m24m01-df instructions doc id 12943 rev 10 21/38 5.2.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 10 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/w bit set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 10 , without acknowledging the byte. note that the address counter value is defined by instructions accessing either the memory or the identification page. when accessing the identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value. when accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory, see section 5.2.1 ) instead of the current address read instruction. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 10 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.3 read identification page (m24m01-d only) the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. the identification page can be read by issuing an read identification page instruction. this instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. the msb address bits a16/a8 are don't care, the lsb address bits a7/a0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g.: when reading the identification page from location 100d, the number of bytes should be less than or equal to 156, as the id page boundary is 256 bytes).
initial delivery state m24m01-r m24m01-df 22/38 doc id 12943 rev 10 5.4 read the lock status (m24m01-d only) the locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. the device returns an acknowledge bit if the identification page is unlocked, otherwise a noack bit if the identification page is locked. right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: start: the truncated command is not executed because the start condition resets the device internal logic, stop: the device is then set back into standby mode by the stop condition. 6 initial delivery state the device is delivered with all bits set to 1 (both in the memory array and in the identification page - that is, each byte contains ffh).
m24m01-r m24m01-df maximum rating doc id 12943 rev 10 23/38 7 maximum rating stressing the device outside the ratings listed in ta bl e 5 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std- 020d (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c v io input or output range ?0.50 v cc +0.6 v i ol dc output current (sda = 0) - 5 ma v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (2) 2. positive and negative pulses applied on different comb inations of pin connect ions, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 ). - 4000 (3) 3. 3000 v for previous devices (process letter a or b). v
dc and ac parameters m24m01-r m24m01-df 24/38 doc id 12943 rev 10 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. figure 11. ac measurement i/o waveform table 6. operating conditions (voltage range r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 mhz table 7. operating conditions (voltage range f) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 mhz table 8. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf scl input rise/fall time, sda input fall time - 50 ns input levels 0.2 v cc to 0.8 v cc v input and output timing reference levels 0.3 v cc to 0.7 v cc v table 9. input parameters symbol parameter (1) 1. sampled only, not 100% tested. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l input impedance (wc ) v in < 0.3 v cc 30 k z h v in > 0.7 v cc 400 k -36 6 ## 6 ## 6 ## 6 ## )nputandoutput 4imingreferencelevels )nputvoltagelevels
m24m01-r m24m01-df dc and ac parameters doc id 12943 rev 10 25/38 table 10. cycling performance by groups of four bytes symbol parameter test condition (1) 1. cycling performance for products identified by process letter k. max. unit ncycle write cycle endurance (2) 2. the write cycle endurance is defined for groups of four data bytes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer. the write cycle endurance is defined by characterization and qualification. ta 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle (3) 3. a write cycle is executed when ei ther a page write, a byte write, a write identification page or a lock identification page instruction is decoded. when usi ng the byte write, the page write or the write identification page, refer also to section 5.1.5: ecc (error corr ection code) and write cycling . ta = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 11. memory cell data retention parameter test co ndition min. unit data retention (1) 1. for products identified by process letter k. the data retention behavior is c hecked in production. the 200- year limit is defined from characterization and qualification results. ta = 55 c 200 year
dc and ac parameters m24m01-r m24m01-df 26/38 doc id 12943 rev 10 . table 12. dc characteristics (m24m01-r, device grade 6) symbol parameter test conditions (in addition to those in table 6 ) min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.8 v, f c = 400 khz 1 (1) 1. devices identified by process letter a or b offer i cc = 0.8 ma ma v cc = 2.5 v, f c =400 khz 1 ma v cc = 5.5 v, f c =400 khz 1.5 (2) 2. the previous product identi fied by process letter a or b was specified with i cc(max) = 2 ma. ma f c = 1 mhz 1.5 (3) 3. devices identified by process letter a or b offer icc = 2.5 ma. ma i cc0 supply current (write) during t w 2 (4)(5) 4. characterized only, not tested in production. 5. the previous product identi fied by process letter a or b was characterized with i cc0(max) = 5 ma. ma i cc1 standby supply current device not selected, v in = v ss or v cc , v cc = 1.8 v 3 (6) 6. devices identified by process letter a or b offer i cc1 = 1 a. a device not selected, v in = v ss or v cc , v cc = 2.5 v 3 (7) 7. devices identified by process letter a or b offer i cc1 = 2 a. a device not selected, v in = v ss or v cc , v cc = 5.5 v 5 (8) 8. devices identified by process letter a or b offer i cc1 = 3 a. a v il input low voltage (scl, sda, wc) 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc < 5.5 v ?0.45 0.30 v cc v v ih input high voltage (scl, sda) 1.8 v v cc < 2.5 v 0.75 v cc v cc +1 v 2.5 v v cc < 5.5 v 0.70 v cc 0 v cc +1 v v ol output low voltage i ol = 1.0 ma, v cc = 1.8 v 0.2 v i ol = 2.1 ma, v cc = 2.5 v 0.4 v i ol = 3.0 ma, v cc = 5.5 v 0.4 v
m24m01-r m24m01-df dc and ac parameters doc id 12943 rev 10 27/38 table 13. dc characteristics (m24m01-f, device grade 6) symbol parameter test conditions (in addition to those in table 6 ) min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.7 v, f c = 400 khz 1 ma v cc = 2.5 v, f c =400 khz 1 ma v cc = 5.5 v, f c =400 khz 1.5 ma f c = 1 mhz 1.5 ma i cc0 supply current (write) during t w 2 (1) 1. characterized only, not tested in production. ma i cc1 standby supply current device not selected, v in = v ss or v cc , v cc = 1.7 v 3a device not selected, v in = v ss or v cc , v cc = 2.5 v 3a device not selected, v in = v ss or v cc , v cc = 5.5 v 5a v il input low voltage (scl, sda, wc) 1.7 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc < 5.5 v ?0.45 0.30 v cc v v ih input high voltage (scl, sda) 1.7 v v cc < 2.5 v 0.75 v cc v cc +1 v 2.5 v v cc < 5.5 v 0.70 v cc 0 v cc +1 v v ol output low voltage i ol = 1.0 ma, v cc = 1.7 v 0.2 v i ol = 2.1 ma, v cc = 2.5 v 0.4 v i ol = 3.0 ma, v cc = 5.5 v 0.4 v
dc and ac parameters m24m01-r m24m01-df 28/38 doc id 12943 rev 10 table 14. 400 khz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 (2) 2. with c l = 10 pf. 300 ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t dxch t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. to avoid spurious start and stop conditions, a minimum delay is plac ed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 (5) 5. the previous product iden tified by process letter p was specified with t clqx = 200 ns (min). both values offer a safe margin compared to the i 2 c specification recommendations. -ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is within the values specified in figure 12 . t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t wldl (7)(1) 7. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (8)(1) 8. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr internal write cycle duration - 5 ms t ns (1) pulse width ignored (input filter on scl and sda) - single glitch -80 (9) 9. the previous product identi fied by process letter a or b was specified with t ns = 100 ns (max). ns
m24m01-r m24m01-df dc and ac parameters doc id 12943 rev 10 29/38 table 15. 1 mhz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 300 - ns t clch t low clock pulse width low 400 - ns t xh1xh2 t r input signal rise time (1) 1. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 120 ns when f c <1mhz. (1) ns t xl1xl2 t f input signal fall time (1) (1) ns t ql1ql2 (8) t f sda (out) fall time - 120 ns t dxcx t su:dat data in setup time 80 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (2) 2. to avoid spurious start and stop conditions, a minimum delay is plac ed between scl=1 and the falling or rising edge of sda. t dh data out hold time 50 - ns t clqv (3) 3. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time consta nt is within the values specified in figure 13 . t aa clock low to next data valid (access time) - 500 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t wldl (4)(8) 4. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (5)(8) 5. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 5 ms t ns (6) 6. characterized only, not tested in production. pulse width ignored (input filter on scl and sda) -80 (7) 7. the previous product identi fied by process letter a or b was specified with t ns = 50 ns (max). ns
dc and ac parameters m24m01-r m24m01-df 30/38 doc id 12943 rev 10 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 13. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz aib "uslinecapacitorp& "uslinepull upresistor k )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! 2 bus # bus ns (ere2 bus # bus ns k ? p& 4he2x#timeconstant mustbebelowthens timeconstantlinerepresented ontheleft bus bus "uslinecapacitorp& "uslinepull upresistork -36 )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! (ere 2 bus # bus ns 2 bu s # bu s ns 4he2 bus # bus timeconstant mustbebelowthens timeconstantlinerepresented ontheleft
m24m01-r m24m01-df dc and ac parameters doc id 12943 rev 10 31/38 figure 14. ac waveforms 3#, 3$!/ut 3#, 3$!)n $atavalid t#,16 t#,18 t#($( 3top condition t#($, 3tart condition 7ritecycle t7 !)g $atavalid t1,1, 3$!)n t#($, 3tart condition t$8#( t#,$8 3$! )nput 3$! #hange t#($( t$($, 3top condition 3tart condition t8(8( 3#, t#(#, t$,#, t#,#( t8(8( t8,8, t8,8, 7# t7,$, t$(7(
package mechanical data m24m01-r m24m01-df 32/38 doc id 12943 rev 10 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 15. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 16. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 0.0256 e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8
m24m01-r m24m01-df package mechanical data doc id 12943 rev 10 33/38 figure 16. so8n ? 8 lead plastic small outli ne, 150 mils body width, package outline 1. drawing is not to scale. table 17. so8n ? 8 lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 1.750 0.0689 a1 0.100 0.250 0.0039 0.0098 a2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 ccc 0.100 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 k 08 08 l 0.400 1.270 0.0157 0.0500 l1 1.040 0.0409 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical data m24m01-r m24m01-df 34/38 doc id 12943 rev 10 figure 17. m24m01 dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package outline 1. drawing is not to scale. 8 aaa 7aferbackside $ % 3ideview $etail! ! ! e e e ' & "umpsside & $etail! 2otated? "ump eee ! 3eatingplane #e?-%?6 e ' b bbb : : 8 ccc- 9 ? : ? ddd- 8 9 : : 2eference /rientation
m24m01-r m24m01-df package mechanical data doc id 12943 rev 10 35/38 table 18. m24m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.540 0.500 0.580 0.0213 0.0197 0.0228 a1 0.190 0.0075 a2 0.350 0.0138 b 0.270 0.0106 d 2.560 2.580 0.1008 0.1016 e 1.698 1.718 0.0669 0.0676 e 1.000 0.0394 e1 0.866 0.0341 e2 0.500 0.0197 e3 0.500 0.0197 f 0.416 0.0164 g 0.780 0.0307 n (number of terminals) 8 8 aaa 0.110 0.0039 bbb 0.110 0.0039 ccc 0.110 0.0039 ddd 0.060 0.0020 eee 0.060 0.0020
part numbering m24m01-r m24m01-df 36/38 doc id 12943 rev 10 10 part numbering table 19. ordering information scheme example: m24m01 - d r mn 6 t p /k device type m24 = i 2 c serial access eeprom device function m01 = 1 mbit (128 kb 8 bits) device family blank: without identification page d: with additional identification page operating voltage r = v cc = 1.8 v to 5.5 v f = v cc = 1.7 v to 5.5 v package mn = so8 (150 mil width) (1) 1. rohs-compliant and halogen-free (ecopack2 ? ) dw = tssop8 (169 mil width) cs = wlcsp (1) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option blank = standard packing t = tape and reel packing plating technology p = ecopack ? (rohs compliant) process (2) 2. the process letters apply to wlcsp devices only. the process letters appear on the device package (marking) and on the shipment box. pl ease contact your nearest st sales office for further information. /k = manufacturing technology code
m24m01-r m24m01-df revision history doc id 12943 rev 10 37/38 11 revision history table 20. document revision history date revision changes 02-may-2011 8 updated features on page 1 . updated figure 3: wlcsp8 connections (bumps side view) , figure 5: maximum rbus value versus bus parasitic capacitance (cbus) for an i2c bus at maximum frequency fc = 400 khz and figure 6: maximum rbus value versus bus parasitic capacitance (cbus) for an i2c bus at maximum frequency fc = 1mhz . updated table 10: dc characteristics (m24m01-r and m24m01-hr) . updated footnote 5 of table 14: ac characteristics at 1 mhz (m24m01-hr) . modified description of write control in section 3.6: write operations . replaced c l with c bus in table 7: ac measurement conditions . changed note 4 about t clqv in table 13: ac characteristics at 400 khz (m24m01-r and m24m01-w) . 23-apr-2012 9 datasheet split into: ? m24m01-r, m24m01-df (this dat asheet) for standard products (range 6), ? m24m01-125 datasheet for aut omotive products (range 3). 26-sep-2012 10 updated: ? section 5.2.2: current address read ? table 2: device select code ? wlcsp package changed layout of features . rephrased some parts of section 5.1.2: page write , section 5.2: read operations , table 10: cycling performance by groups of four bytes and table 11: memory ce ll data retention .
m24m01-r m24m01-df 38/38 doc id 12943 rev 10 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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